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Operational Evaluation of Network on Chip Topologies
Ana Kumar#1, Shivam Tyagi*2, C.K. Jha#3

Published in: Journal for Advance Research in Applied Sciences
Volume- 5, Issue-1, pp.16-22, Jan 2018
DPI :-> 16.10089.JARAS.2018.V5I1.1622.2275



Abstract
The Network on Chip (NoC) has developed as a substitute for wired or interconnection network for System on Chip (SoC). It acts as a way to reduce existing problems of interference, bandwidth desideratum, and potential and makes clock distribution work easier. The performance of the network can be evaluated by numerous factors but latency and throughput are primary characteristics of measurement. So, this paper contains study and evaluation of various existing topologies and their operational evaluation is done on the basis of latency and throughput.

Key-Words / Index Term
operational

How to cite this article
Ana Kumar#1, Shivam Tyagi*2, C.K. Jha#3 , “Operational Evaluation of Network on Chip Topologies”, Journal for Advance Research in Applied Sciences, 5, Issue-1, pp.16-22, Jan 2018. DPI:16.10089.JARAS.V5.I1.2275