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A novel design methodology of 1-bit hybrid full adder using SVL Technique
Vipin Kumar Shrivas#1, Shyam Akashe*2

Published in: Journal for Advance Research in Applied Sciences
Volume- 4, Issue-7, pp.329-333, Dec 2017
DPI :-> 16.10089.JARAS.2017.V4I7.329333.2256



Abstract
In this paper, we are presenting a hybrid 1-bit full adder. Hiring to each one like transmission gate logic and complementary metal-oxide-semiconductor (CMOS) logic. we are operating the purposed circuit with the help of cadence virtuoso tool in 45-nm technology of software. The performance parameter of the circuit such as power and delay are compared with the 16t full adder design for 1.8-V supply at 180nm and for 1.2-V supply at 90-nm technology. For 0.7-V supply at45-nm technology, the average power consumption (0.07689µW) was found to be exceptionally low with average low delay (0.00136PS) ensuing from the intentional incorporation of extremely weak COM. The propose was supplementary extensive for implementing 32- bit full adder moreover, the power at 180-nm technology for the 1.8-v power supply voltage and 2.45-ns delay and 53.36µW power at 90-nm technology for 1.2-v power supply voltage. If we meet our result with any other old method, then we get a lot of difference in our today's outcome, whether it is speed or power and delay.

Key-Words / Index Term
Hbrid full adder, low power, high speed.

How to cite this article
Vipin Kumar Shrivas#1, Shyam Akashe*2 , “A novel design methodology of 1-bit hybrid full adder using SVL Technique”, Journal for Advance Research in Applied Sciences, 4, Issue-7, pp.329-333, Dec 2017. DPI:16.10089.JARAS.V4.I7.2256