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Implementation of Hybrid 4-1 Mux Architecture on FPGA
SUPRAJA PAMIDI1, G. NAGARAJU2, JENNE HANUMANTHU 3

Published in: Journal for Advance Research in Applied Sciences
Volume- 4, Issue-7, pp.1-7, Dec 2017
DPI :-> 16.10089.JARAS.2017.V4I7.17.2200



Abstract
Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid Configurable logic block architectures, both non fracturable and fracturable with varying MUX: LUT logic element ratios are evaluated across two benchmark suites (VTR and CH Stone) using a custom tool flow consisting of Leg Up-HLS, Odin-II front- end synthesis, ABC logic synthesis and technology mapping, and VPR for packing, placement, routing, and architecture exploration. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Experimentally, we show that for non fracturable architectures, without any mapper optimizations, we naturally save up to ~8% area post place and route; both accounting for complex logic block and routing area while maintaining mapping depth. With architecture-aware technology mapper optimizations in ABC, additional area is saved, post-place-and-route. For factorable architectures, experiments show that only marginal gains are seen after place-and-route up to ~2%. For both non factorable and factorable architectures, we see minimal impact on timing performance for the architectures with best area-efficiency.

Key-Words / Index Term
FPGAs, LUTs, MUXs, CAD

How to cite this article
SUPRAJA PAMIDI1, G. NAGARAJU2, JENNE HANUMANTHU 3 , “Implementation of Hybrid 4-1 Mux Architecture on FPGA”, Journal for Advance Research in Applied Sciences, 4, Issue-7, pp.1-7, Dec 2017. DPI:16.10089.JARAS.V4.I7.2200