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Sreenivasulu Pasupuleti [1] , C.Pakkiraiah [2]

Published in: Journal for Advance Research in Applied Sciences
Volume- 4, Issue-1, pp.582-587, Jun 2017
DPI :-> 16.10089.JARAS.2017.V4I1.582587.1793

The multiplier is one of the basic functions used in various VLSI applications. The primary issues in the design of multiplier cell are area, delay and power dissipation. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. Different types of multipliers are available in the previous depending upon the requirements and various companies are using different types of multipliers according to their needs. In this paper we used new 4 bit multiplier.Gate Diffusion Input (GDI) with level restoration has the conductance overlap between NMOS and PMOS devices so providing high short circuit power dissipation and providing low Output Voltage VoH. Further to reduce the number of transistors and power in SRL-GDI based full adder, the self-resetting logic with modified gate diffusion input logic (SRL-MGDI) is proposed to achieve the low area, low power and high speed. Comparison between SRL-GDI and SRL-MGDI is performed to analysis the circuit functionality in precharge and evaluate paths and simulated in tanner 45nm technology process. The circuit is designed by using tanner toolv13.0.

Key-Words / Index Term
Self-Resetting Logic; Gate Diffusion Input Technique; Full adders.

How to cite this article
Sreenivasulu Pasupuleti [1] , C.Pakkiraiah [2] , “DESIGN OF NOVEL 4-BIT MULTIPLIER CIRCUIT BY USING SELF RESETTING MODIFIED GDI LOGIC (SR-MGDIL) ”, Journal for Advance Research in Applied Sciences, 4, Issue-1, pp.582-587, Jun 2017. DPI:16.10089.JARAS.V4.I1.1793