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A LOW POWER DFT BASED CMOS RECEIVER WITH DUAL USE OF POWER LINES
B.JEEVITHESWARI1, S.KARIMULLAH2

Published in: Journal for Advance Research in Applied Sciences
Volume- 4, Issue-1, pp.550-557, Jun 2017
DPI :-> 16.10089.JARAS.2017.V4I1.550557.1788



Abstract
Smart Grids are becoming a reality all over the world. Nowadays, the research efforts for the introduction and deployment of these grids are mainly focused on the development of the field of Smart Metering. This emerging application requires the use of technologies to access the significant number of points of supply (PoS) existing in the grid, covering the Low Voltage (LV) segment with the lowest possible costs. Power Line Communications (PLC) has been extensively used in electricity grids for a variety of purposes and, of late, has been the focus of renewed interest. PLC is really well suited for quick and inexpensive pervasive deployments. However, no LV grid is the same in any electricity company (utility), and the particularities of each grid evolution, architecture, circumstances and materials, makes it a challenge to deploy Smart Metering networks with PLC technologies, with the Smart Grid as an ultimate goal. This paper covers the evolution of Smart Metering networks, together with the evolution of PLC technologies until both worlds have converged to project PLC-enabled Smart Metering networks towards Smart Grid. This paper develops guidelines over a set of strategic aspects of PLC Smart Metering network deployment based on the knowledge gathered on real field; and introduces the future challenges of these networks in their evolution towards the Smart Grid.

Key-Words / Index Term
Design-for-testability (DFT), PLC at ICs, PLC receiver, power line communications (PLCs).

How to cite this article
B.JEEVITHESWARI1, S.KARIMULLAH2 , “A LOW POWER DFT BASED CMOS RECEIVER WITH DUAL USE OF POWER LINES ”, Journal for Advance Research in Applied Sciences, 4, Issue-1, pp.550-557, Jun 2017. DPI:16.10089.JARAS.V4.I1.1788