Flash News
Journal evaluation report (Journal Citation Reference (JCR) ) will be declared on the last week of January 2018 Submit your Journal to get JCR-R Indexing and Impact Factor

Publisher Login

Latest News
Welcome to IARC- JCR Report

Submit your Journal to get IARC-JCRR Indexing and Impact Factor
 

Impact Factor calculated by IARC on the basis of Journal Citation Reference (JCR) Report.

 

Contact: iarcdpi@gmail.com

 

FPGA IMPLEMENTATION OF COMPRESSING TECHNIQUE IN VLSI MULTIPLIERS FOR FFT ARCHITECTURES
L.Malathi, S.Munaf, Dr.A.Bharahi, Dr. A.N.Jayanthi

Published in: International Journal of Current Engineering And Scientific Research ( IJCESR)
Volume- 4, Issue-11, pp.68-72, Nov 2017
DPI :-> 16.10046.IJCESR.2017.V4I11.6872.2190



Abstract
Compressors are used for less power consumption and high throughput. By analyses the compression techniques the fast and reduced delay were achieved. In the proposed system necessary power was reduced compared to the existing multipliers with an accurate level. The proposed system can be used in digital image processing and communication related applications where compression in multipliers is needed. Nth order compression is used in this proposed.

Key-Words / Index Term
Nth order compressor, Multiplier

How to cite this article
L.Malathi, S.Munaf, Dr.A.Bharahi, Dr. A.N.Jayanthi , “FPGA IMPLEMENTATION OF COMPRESSING TECHNIQUE IN VLSI MULTIPLIERS FOR FFT ARCHITECTURES”, International Journal of Current Engineering And Scientific Research ( IJCESR), 4, Issue-11, pp.68-72, Nov 2017. DPI:16.10046.IJCESR.V4.I11.2190