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SYNTHESIS & OPTIMIZATION OF ASYNCHRONOUS PROCESSOR USING XILINX ISE & VIVADO
Archana rani, Dr. Naresh Grover

Published in: International Journal of Current Engineering And Scientific Research ( IJCESR)
Volume- 4, Issue-11, pp.31-39, Nov 2017
DPI :-> 16.10046.IJCESR.2017.V4I11.3139.2184



Abstract
As the technology era has been changing, the designing pattern of an IC is also changing. An IC designing is now divided into two definite fields i.e. Front-End design and BackEnd design. The Front-End design is using HDLs (Hardware Description Languages i.e. VHDL or Verilog) and the verification of those ICs, whereas the Back-End Design is related to the Physical Design techniques. But both of the IC design techniques required some extra efforts in terms of their Speed, Shape, and Size, which needs the Optimization efforts. This paper deals with the area and power optimization efforts in terms of the logic utilization by using XST & Vivado Tools. These efforts are going to apply on the previously designed 32-bit Asynchronous Processor using HDLs written by Archana Rani et al. After applying area optimization techniques i.e. Logic Optimization, LUT mapping and Resource Sharing etc. the reasonable results in terms of power and area utilization has been achieved.

Key-Words / Index Term
FPGA Based System Design, Design Optimization, Xilinx Synthesis Tool (XST) and Vivado.

How to cite this article
Archana rani, Dr. Naresh Grover , “SYNTHESIS & OPTIMIZATION OF ASYNCHRONOUS PROCESSOR USING XILINX ISE & VIVADO”, International Journal of Current Engineering And Scientific Research ( IJCESR), 4, Issue-11, pp.31-39, Nov 2017. DPI:16.10046.IJCESR.V4.I11.2184