Flash News
Welcome to IARC

Publisher Login

Latest News
Welcome to IARC- JCR Report

Submit your Journal to get IARC-JCRR Indexing and Impact Factor
 

Impact Factor calculated by IARC on the basis of Journal Citation Reference (JCR) Report.

 

Contact: iarcdpi@gmail.com

 

AN INNOVATIVE APPROACH FOR ASYNCHRONOUS MICROPROCESSOR DESIGN BASED ON FPGA
Archana Rani, Dr. Naresh Grover

Published in: International Journal of Current Engineering And Scientific Research ( IJCESR)
Volume- 4, Issue-11, pp.21-30, Nov 2017
DPI :-> 16.10046.IJCESR.2017.V4I11.2130.2183



Abstract
As the efficiency and power consumption plays an important role in electronic system design, an asynchronous design is used to reduce such challenges faced in synchronous architectures. The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper deals with the novel design and implementation of such type of asynchronous microprocessor by using VHDL on Xilinx ISE tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.

Key-Words / Index Term
Asynchronous design, Processor, VHDL, MIPS, Synthesis & Simulation, Instruction data path, EDA Tools

How to cite this article
Archana Rani, Dr. Naresh Grover , “AN INNOVATIVE APPROACH FOR ASYNCHRONOUS MICROPROCESSOR DESIGN BASED ON FPGA”, International Journal of Current Engineering And Scientific Research ( IJCESR), 4, Issue-11, pp.21-30, Nov 2017. DPI:16.10046.IJCESR.V4.I11.2183