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Ch.Pallavi, M.Niraja, N.Revathi

Published in: International Journal of Current Engineering And Scientific Research ( IJCESR)
Volume- 4, Issue-10, pp.7-16, Oct 2017
DPI :-> 16.10046.IJCESR.2017.V4I10.716.2078

Testing of low power in very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This paper mainly focuses on reducing the power consumption during testing of the VLSI design circuits. So Power consumption in test becomes a higher barrier for VLSI to design combinational circuit, during test mode as in its normal mode of functioning seriously affects the chip reliability. There are many techniques are introduced to reduce the test power. Usually the power dissipation is due to the sequential and combinational elements presents in the circuit. In this paper proposed different methodologies and they are at cell level optimization to reduce test power. Gating techniques are proposed to reduce the power in combinational circuits. This paper propose a novel scan cell architecture for low power scan based technique with powerefficiency that provides combined solution for reducing total average power in both combinational part and scan cell. The proposed scan cell reduces the number of transitions during shift and capture mode. The proposed method is implemented with different combinational circuits and the experimental results were observed. Simulation results have shown that the proposed gating scan cell save 20-25% total average power in shift and capture mode as compared to conventional scan cell.

Key-Words / Index Term
Power consumption, Low power testing, Gating technique, combinational circuits, VLSI.

How to cite this article
Ch.Pallavi, M.Niraja, N.Revathi , “A GATING SCAN CELL ARCHITECTURE FOR TEST POWER REDUCTION IN VLSI CIRCUITS”, International Journal of Current Engineering And Scientific Research ( IJCESR), 4, Issue-10, pp.7-16, Oct 2017. DPI:16.10046.IJCESR.V4.I10.2078