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VLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER
Dr. S.Satheeskumaran, K. Sasikala

Published in: International Journal of Current Engineering And Scientific Research ( IJCESR)
Volume- 4, Issue-10, pp.59-66, Oct 2017
DPI :-> 16.10046.IJCESR.2017.V4I10.5966.2071



Abstract
Digital FIR filter is popularly used in Signal Processing for noise removal and related applications. In this paper, we present Modified Distributed Arithmetic (DA) Based Digital FIR filter that consumes less power than the existing digital filters. Modified DA architecture is proposed using register reuse technique. We designed an 8 tap 16 bit programmable coefficient digital finite impulse response (FIR) filter for solving the high power consumption issues. The filter output is realized through a series of delays, multipliers and adders. To realize in hardware, the design was implemented in Cadence Design Tools such as NCLaunch, RTL compiler, SoC Encounter. SoC encounter generates a GDSII file which gives detailed specification for manufacturing the semi-custom design. Our design has been simulated using Verilog hardware descriptive language. The measured maximum clock speed is 70 MHz and the total die area is 0.66 mm2. The total power consumed is 23mW which is low compared to the existing designs.

Key-Words / Index Term
FIR filter, SoC Encounter, Verilog HDL, multipliers, adders.

How to cite this article
Dr. S.Satheeskumaran, K. Sasikala , “VLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER”, International Journal of Current Engineering And Scientific Research ( IJCESR), 4, Issue-10, pp.59-66, Oct 2017. DPI:16.10046.IJCESR.V4.I10.2071