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AN AREA EFFICIENT NETWORK ON CHIP ARCHITECTURE FOR CLASSICAL AND NETWORK BASED METHODOLOGIES
N.Nandhagopal , S.Navaneethan, R.Kandasamy

Published in: International Journal of Current Engineering And Scientific Research ( IJCESR)
Volume- 4, Issue-10, pp.24-28, Oct 2017
DPI :-> 16.10046.IJCESR.2017.V4I10.2428.2080



Abstract
The increasing complexity of modern digital devices demands for ever increasing communication requirements, and for an ever increasing heterogeneity of the target applications. Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communication requirements in heterogeneous digital systems. Classical design approaches, such as bus-based systems or point-to-point connections, are no longer suitable for highly integrated systems since they lack of flexibility and scalability with the increasing number of modules attached to the system. Nevertheless, NoC-based interconnects require additional design efforts and, in general, major resource requirements as compared to classical bus-based systems. Such an issue can be solved by directly optimizing over the different design factors. Integration of NoC (Network on Chip) architecture with Classical Bus based systems can be employed to overcome the disadvantages of both Classical and Network based methodologies. The efficiency of the proposed methodology is shown by comparing with existing methodology, taking directly into consideration the resource requirements of the target FPGA device.

Key-Words / Index Term
of the target FPGA device. Keywords: Network on Chip, Field Programmable Gate Array, Communication, System on Chip.

How to cite this article
N.Nandhagopal , S.Navaneethan, R.Kandasamy , “AN AREA EFFICIENT NETWORK ON CHIP ARCHITECTURE FOR CLASSICAL AND NETWORK BASED METHODOLOGIES”, International Journal of Current Engineering And Scientific Research ( IJCESR), 4, Issue-10, pp.24-28, Oct 2017. DPI:16.10046.IJCESR.V4.I10.2080